`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:39:14 04/19/2014 
// Design Name: 
// Module Name:    startscreen 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module startscreen (vgadisp,hcounter, vcounter,blank);

	
	
	output reg vgadisp;
	input blank;
	input [10:0] hcounter, vcounter;
	
	
always@(*)	begin

	vgadisp= ~blank &&
	(vcounter>= 160 && vcounter<180 && hcounter>=220 && hcounter< 260) || (vcounter>= 180 && vcounter<220 && hcounter>=220 && hcounter< 240) || (vcounter>= 220 && vcounter<240 
	&& hcounter>=220 && hcounter< 260);
end


/*4'd2: begin
vgadisp=~blank &&
(vcounter>= 47 && vcounter<56 && hcounter>=432 && hcounter< 456) ||(vcounter>= 65 && vcounter<74 && hcounter>=432 && hcounter< 456)
			||(vcounter>= 83 && vcounter<92 && hcounter>=432 && hcounter< 456)
			||(vcounter>= 56 && vcounter<65 && hcounter>=450 && hcounter< 456)
		||(vcounter>= 74 && vcounter<83 && hcounter>=432 && hcounter< 438);
end   */

end
endmodule

